Language
High-Level Synthesis of Digital Circuits
Enrollment period
Mode of delivery
Course study period
Price
Course is free.
Education information
1. ASIC and FPGA Design and Synthesis Flow Overview
2. Theory of High-Level Synthesis
3. HLS Languages, Tools, and Design and Verification Flow
4. Microarchitecture Optimization I: Loop Handling
5. Microarchitecture Optimization II: Array Handling
6. Microarchitecture Optimization III: Data-Path Optimization
7. Interface Synthesis
8. Practical HLS Case Study
Education format
Semester
Academic Year 2022-2023
Discipline
Course organiser
Location
Prerequisities and co-requisites
Contact information
More information and contact information
Registration
Registration for the training is submitted by applying for non-degree study right. The application is submitted in e-Forms (Electronic forms of the University of Oulu).
- Register for the training module by clicking ”Apply for non-degree study right” at the top of the page.
- The link redirects you to the main page of e-Forms . You can log in with Suomi.fi identification.
- After logging in to e-Forms, click form "2.Application for non-degree studies".
- Please fill in "Personal data" and "Study right" section.
- In the Workflow section at the bottom of the page, please select a “Next assignee”.
You are informed of a granted non-degree study right through e-mail.
The University of Oulu reserves the rights to any changes.